248 Publications (Page 6 of 10)
2000
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 16, (no. 5), pp. 403-404, Oct 2000.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 16, (no. 4), pp. 315, Aug 2000.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 16, (no. 3), pp. 163, Jun 2000.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 16, (no. 6), pp. 571, Dec 2000.
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False-Path Removal Using Delay Fault SimulationGharaybeh, Marwan⋅Agrawal, Vishwani⋅Bushnell, Michael and Parodi, CarlosJournal of Electronic Testing : (JETTA), vol. 16, (no. 5), pp. 463-476, Oct 2000.
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Improving path delay testability of sequential circuitsChakraborty, T. J⋅Agrawal, Vishwani D and Bushnell, M. LIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, (no. 6), pp. 736-741, 2000.
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Line coverage of path delay faultsMajhi, Ananta K⋅Agrawal, Vishwani D⋅Jacob, James and Patnaik, Lalit MIEEE TRANS VERY LARGE SCALE INTEGR VLSI SYST, vol. 8, (no. 5), pp. 610-614, 2000.
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Path delay fault simulation of sequential circuitsChakraborty, T. J⋅Agrawal, Vishwani D and Bushnell, MichaelIEEE TRANS VERY LARGE SCALE INTEGR VLSI SYST, vol. 8, (no. 2), pp. 223-228, 2000.
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Reducing the complexity of defect level modeling using the clustering effectde Sousa, Jose T and Agrawal, Vishwani DDesign, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 27-30 Mar. 2000. 2000.
| Conference Proceeding
1999
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 15, (no. 3), pp. 215, Dec 1999.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 15, (no. 1-2), pp. 5, Aug 1999.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 14, (no. 1-2), pp. 7, Feb 1999.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 14, (no. 3), pp. 187-188, Jun 1999.
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On the guaranteed failing and working frequencies in path delay fault analysisPeng, Qiang⋅Agrawal, Vishwani D and Savir, JacobCONF REC IEEE INSTRUM MEAS TECHNOL CONF, vol. 3, pp. 1794-1799, 1999.
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1998
A rated-clock test method for path delay faultsBose, S.⋅Agrawal, Prathima and Agrawal, Vishwani DIEEE TRANS VERY LARGE SCALE INTEGR VLSI SYST, vol. 6, (no. 2), pp. 323-331, 1998.
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Deriving logic systems for path delay test generationBose, S.⋅Agrawal, Prathima and Agrawal, Vishwani DIEEE Transactions on Computers, vol. 47, (no. 8), pp. 829-846, 1998.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 12, (no. 3), pp. 167, Jun 1998.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 12, (no. 1-2), pp. 5, Feb 1998.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 13, (no. 3), pp. 219, Dec 1998.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 13, (no. 2), pp. 75, Oct 1998.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 13, (no. 1), pp. 5, Aug 1998.
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False-path removal using delay fault simulationGharaybeh, Marwan A⋅Agrawal, Vishwani D and Bushnell, Michael LThe 1998 7th Asian Test Symposium; Singapore; Singapore; 02-04 Dec. 1998. 1998.
| Conference Proceeding
Path-status graph with application to delay fault simulationGharaybeh, Marwan A⋅Bushnell, Michael and Agrawal, Vishwani DIEEE TRANS COMPUT AIDED DES INTEGR CIRCUITS SYST, vol. 17, (no. 4), pp. 324-332, 1998.
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Statistical delay fault coverage estimation for synchronous sequential circuitsPappu, Lakshminarayana⋅Bushnell, Michael⋅Agrawal, Vishwani D and Mandyam-Komar, SrinivasJ ELECTRON TEST THEORY APPL JETTA, vol. 12, (no. 3), pp. 239-254, 1998.
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1997
Adder and comparator synthesis with exclusive-OR transform of inputsJacob, J.⋅Sivakumar, P. S and Agrawal, Vishwani DThe 1997 10th International Conference on VLSI Design; Hyderabad; India; 04-07 Jan. 1997. 1997.
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