248 Publications (Page 4 of 10)
2008
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 24, (no. 1-3), pp. 1, Jun 2008.
| Journal Article
2007
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 23, (no. 6), pp. 465, Dec 2007.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 23, (no. 2-3), pp. 111, Jun 2007.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 23, (no. 5), pp. 369, Oct 2007.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 23, (no. 1), pp. 5, Feb 2007.
| Journal Article
Graphical IDDQ Signatures Reduce Defect Level and Yield LossRao, L.⋅Bushnell, Michael and Agrawal, Vishwani DIEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, (no. 11), 2007.
| Journal Article
2006
CMOS Leakage and Glitch Minimization for Power-Performance TradeoffLu, Yuanlin and Agrawal, Vishwani DJournal of Low Power Electronics, vol. 2, (no. 3), pp. 378-387, 2006.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 22, (no. 4-6), pp. 307, Dec 2006.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 22, (no. 1), pp. 5, Feb 2006.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 22, (no. 2), pp. 111, Apr 2006.
| Journal Article
Input-specific dynamic power optimization for VLSI circuitsHu, Fei and Agrawal, Vishwani DInternational Symposium on Low Power Electronics and Design: Proceedings of the 2006 international symposium on Low power electronics and design; 04-06 Oct. 2006. 2006.
| Conference Proceeding
Transistor Sizing of Logic Gates to Maximize Input Delay VariabilityRaja, Tezaswi⋅Agrawal, Vishwani D and Bushnell, Michael LJournal of Low Power Electronics, vol. 2, (no. 1), pp. 121-128, 2006.
| Journal Article
2005
Combinational automatic test pattern generation for acyclic sequential circuitsKim, Yong C⋅Agrawal, Vishwani D and Saluja, Kewal KIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, (no. 6), pp. 948-956, 2005.
| Journal Article
Diagnostic and Detection Fault Collapsing for Multiple Output CircuitsSandireddy, Raja K and Agrawal, Vishwani DDesign, Automation, and Test in Europe: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2; 07-11 Mar. 2005. 2005.
| Conference Proceeding
Dual-transition glitch filtering in probabilistic waveform power estimationHu, Fei and Agrawal, Vishwani DGreat Lakes Symposium on VLSI: Proceedings of the 15th ACM Great Lakes symposium on VLSI; 17-19 Apr. 2005. 2005.
| Conference Proceeding
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 21, (no. 5), pp. 459, Oct 2005.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 21, (no. 1), pp. 5, Feb 2005.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 21, (no. 2), pp. 111, Apr 2005.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 21, (no. 3), pp. 199, Jun 2005.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 21, (no. 6), pp. 567, Dec 2005.
| Journal Article
2004
A new classification of path-delay fault testability in terms of stuck-at faultsMajumder, Subhashis⋅Bhattacharya, Bhargab B⋅Agrawal, Vishwani D and Bushnell, Michael LJournal of Computer Science and Technology, vol. 19, (no. 6), pp. 955-964, 2004.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 20, (no. 2), pp. 127, Apr 2004.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 20, (no. 1), pp. 5-6, Feb 2004.
| Journal Article
EditorialAgrawal, Vishwani DJournal of Electronic Testing : (JETTA), vol. 20, (no. 6), pp. 571, Dec 2004.
| Journal Article
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 20, (no. 3), pp. 219, Jun 2004.
| Journal Article
