248 Publications (Page 5 of 10)
2004
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 20, (no. 1), pp. 5-6, Feb 2004.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 20, (no. 2), pp. 127, Apr 2004.
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2003
A test evaluation technique for VLSI circuits using register-transfer level fault modelingThaker, PA⋅Agrawal, Vishwani D and Zaghloul, Mona EIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, (no. 8), 2003.
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EditorialAgrawal, VdJournal of Electronic Testing : (JETTA), vol. 19, (no. 5), pp. 495, Oct 2003.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 19, (no. 6), pp. 607, Dec 2003.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 19, (no. 4), pp. 363, Aug 2003.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 19, (no. 1), pp. 5, Feb 2003.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 19, (no. 2), pp. 95, Apr 2003.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 19, (no. 3), pp. 219, Jun 2003.
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2002
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 3), pp. 255, Jun 2002.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 6), pp. 567-568, Dec 2002.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 1), pp. 5, Feb 2002.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 2), pp. 103-104, Apr 2002.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 4-5), pp. 359, Aug 2002.
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Multiple Faults:Modeling, Simulation and TestKim, Yong C⋅Saluja, Kewal K and Agrawal, Vishwani Dwith EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design; 07-11 Jan. 2002. 2002.
| Conference Proceeding
State and Fault Information for Compaction-Based Test GenerationGiani, Ashish⋅Sheng, Shuo⋅Hsiao, Michael and Agrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 18, (no. 1), pp. 63-72, Feb 2002.
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2001
EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 17, (no. 2), pp. 79, Apr 2001.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 17, (no. 3-4), pp. 203, Jun 2001.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 17, (no. 6), pp. 455, Dec 2001.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 17, (no. 5), pp. 367, Oct 2001.
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Efficient spectral techniques for sequential ATPGGiani, A.⋅Sheng, S.⋅Hsiao, Michael S and Agrawal, Vishwani DDesign, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe. 2001.
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2000
A testability metric for path delay faults and its applicationTsai, Huan-Chih⋅Cheng, Kwang Ting ( and Agrawal, Vishwani Dwith EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2000 conference on Asia South Pacific design automation. 2000.
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Choice of tests for logic verification and equivalence checking and the use of fault simulationAgrawal, Vishwani DThe 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium; Calcutta; India; 03 Jan.-07 Jan. 2000. 2000.
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Compaction-based test generation using state and fault informationGiani, Ashish⋅Sheng, Shuo⋅Hsiao, Michael S and Agrawal, Vishwani DPROC ASIAN TEST SYMP. pp. 159-164. 2000, 2000.
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EditorialAgrawal, VishwaniJournal of Electronic Testing : (JETTA), vol. 16, (no. 1-2), pp. 5, Feb 2000.
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