248 Publications (Page 8 of 10)
1995
Asynchronous algorithm for sequential circuit test generation on a network of workstations
Sienicki, James⋅Bushnell, Michael⋅Agrawal, Prathima and Agrawal, Vishwani D
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995. 1995. | Conference Proceeding
 
Classification and test generation for path-delay faults using single stuck-fault tests
Gharaybeh, Marwan A⋅Bushnell, Michael and Agrawal, Vishwani D
The 1995 26th International Test Conference; Washington, DC; USA; 21-25 Oct. 1995. 1995. | Conference Proceeding
 
Combinational ATPG theorems for identifying untestable faults in sequential circuits
Agrawal, Vishwani D and Chakradhar, S. T
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, (no. 9), pp. 1155-1160, 1995. | Journal Article
 
Efficient automatic test generation system for path delay faults in combinational circuits
Majhi, Ananta K⋅Jacob, James⋅Patnaik, Lalit M and Agrawal, Vishwani D
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995. 1995. | Conference Proceeding
 
Energy models for delay testing
Chakradhar, Srimat T⋅Iyer, Mahesh A and Agrawal, Vishwani D
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, (no. 6), pp. 728-739, 1995. | Journal Article
 
Functional test generation for non-scan sequential circuits
Srinivas, M. K⋅Jacob, James and Agrawal, Vishwani D
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995. 1995. | Conference Proceeding
 
High-performance circuit testing with slow-speed testers
Agrawal, Vishwani D and Chakraborty, Tapan J
The 1995 26th International Test Conference; Washington, DC; USA; 21-25 Oct. 1995. 1995. | Conference Proceeding
 
Robust testing for stuck-at faults
Chakraborty, Tapan J and Agrawal, Vishwani D
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995. 1995. | Conference Proceeding
 
Statistical methods for delay fault coverage analysis
Heragu, Keerthi⋅Agrawal, Vishwani D and Bushnell, Michael L
The 8th International Conference on VLSI Design; New Delhi; India; 04-07 Jan. 1995. 1995. | Conference Proceeding
 
Test generation for path delay faults using binary decision diagrams
Bhattacharya, D.⋅Agrawal, Prathima and Agrawal, Vishwani D
IEEE Transactions on Computers, vol. 44, (no. 3), pp. 434-447, 1995. | Journal Article
1994
An efficient path delay fault coverage estimator
Heragu, Keerthi⋅Bushnell, Michael and Agrawal, Vishwani D
Annual ACM IEEE Design Automation Conference: Proceedings of the 31st annual conference on Design automation; 06-10 June 1994. 1994. | Conference Proceeding
 
An exact algorithm for selecting partial scan flip-flops
Chakradhar Srimat, T.⋅Balakrishnan, Arun and Agrawal, Vishwani D
Annual ACM IEEE Design Automation Conference: Proceedings of the 31st annual conference on Design automation; 06-10 June 1994. 1994. | Conference Proceeding
 
Built-in self-test for digital integrated circuits
Agrawal, Vishwani D⋅Lin, Chih-Jen⋅Rutkowski, Paul W⋅Wu, Shianling and Zorian, Yervant
AT&T TECH J, vol. 73, (no. 2), pp. 30-39, 1994. | Journal Article
 
Efficient path delay fault coverage estimator
Heragu, Keerthi⋅Bushnell, Michael and Agrawal, Vishwani D
PROC DES AUTOM CONF, pp. 516-521, 1994. | Journal Article
 
Exact algorithm for selecting partial scan flip-flops
Chakradhar, Srimat T⋅Balakrishnan, Arun and Agrawal, Vishwani D
PROC DES AUTOM CONF, pp. 81-86, 1994. | Journal Article
1993
Accurate computation of field reject ratio based on fault latency
Das, D.⋅Seth, Sharad C and Agrawal, Vishwani D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, (no. 4), pp. 537-545, 1993. | Journal Article
 
A tutorial on built-in self-test. 2. Applications
Agrawal, Vishwani D⋅Kime, C. R and Saluja, Kewal K
IEEE Design & Test of Computers, vol. 10, (no. 2), pp. 69-77, 1993. | Journal Article
 
Design for testability for path delay faults in sequential circuits
Chakraborty, Tapan J⋅Agrawal, Vishwani D and Bushnell, Michael L
Annual ACM IEEE Design Automation Conference: Proceedings of the 30th international conference on Design automation; 14-18 June 1993. 1993. | Conference Proceeding
 
Finite state machine synthesis with fault tolerant test function.
Chakradhar, Srimat T⋅Kanjilal, Suman and Agrawal, Vishwani D
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 4, (no. 1), pp. 57-69, 1993. | Journal Article
 
Generating tests for delay faults in nonscan circuits
Agrawal, Prathima⋅Agrawal, Vishwani D and Seth, Sharad C
IEEE Design & Test of Computers, vol. 10, (no. 1), pp. 20-28, 1993. | Journal Article
 
Generation of compact delay tests by multiple path activation.
Bose, Soumitra⋅Agrawal, Prathima and Agrawal, Vishwani D
PROC INT TEST CONF., 1993. | Journal Article
 
Logic systems for path delay test generation.
Bose, Soumitra⋅Agrawal, Prathima and Agrawal, Vishwani D
IEEE, 1993. | Journal Article
 
Optimistic update theorem for path delay testing in sequential circuits.
Bose, Soumitra⋅Agrawal, Prathima and Agrawal, Vishwani D
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 4, (no. 3), pp. 285-290, 1993. | Journal Article
 
Path delay fault simulation of sequential circuits
Bose, Soumitra⋅Agrawal, Prathima and Agrawal, Vishwani D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, (no. 4), pp. 453-461, 1993. | Journal Article
 
Sequential circuit test generation on a distributed system
Agrawal, Prathima⋅Agrawal, Vishwani D and Villoldo, J.
Annual ACM IEEE Design Automation Conference: Proceedings of the 30th international conference on Design automation; 14-18 June 1993. 1993. | Conference Proceeding