248 Publications (Page 10 of 10)
1990
Toward massively parallel automatic test generation
Chakradhar, S. T⋅Bushnell, Michael and Agrawal, Vishwani D
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, (no. 9), pp. 981-994, 1990. | Journal Article
1989
A directed search method for test generation using a concurrent simulator
Agrawal, Vishwani D⋅Cheng, Kwang-Ting and Agrawal, Prathima
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, (no. 2), pp. 131-138, 1989. | Journal Article
1988
Contest:a concurrent test generator for sequential circuits
Agrawal, Vishwani D⋅Cheng, Kwang-Ting and Agrawal, Prathima
Annual ACM IEEE Design Automation Conference: Proceedings of the 25th ACM/IEEE conference on Design automation; 12-15 June 1988. 1988. | Conference Proceeding
 
Formal verification of digital circuits using hybrid simulation
Srinivas, N. C and Agrawal, Vishwani D
IEEE Circuits and Devices Magazine, vol. 4, (no. 1), pp. 19-27, 1988. | Journal Article
 
LSI product quality and fault coverage
Agrawal, Vishwani D⋅Seth, S. C and Agrawal, Prathima
Annual ACM IEEE Design Automation Conference: Papers on Twenty-five years of electronic design automation. 1988. | Conference Proceeding
1987
A complete solution to the partial scan problem.
Agrawal, Vishwani D⋅Cheng, K-T⋅Johnson, D. D and Lin, T.
INTERNATIONAL TEST CONFERENCE 1987., 1987. | Journal Article
1985
Cutting Chip-Testing Costs
Seth, Sharad C and Agrawal, Vishwani D
IEEE Spectrum, vol. 22, (no. 4), pp. 38, Apr 1985. | Journal Article
 
Multiple output minimization
Agrawal, Prathima⋅Agrawal, Vishwani D and Biswas, Nripendra N
Annual ACM IEEE Design Automation Conference: Proceedings of the 22nd ACM/IEEE conference on Design automation. 1985. | Conference Proceeding
1984
A gate level model for CMOS combinational logic circuits with application to fault detection
Reddy, Sudhakar M⋅Agrawal, Vishwani D and Jain, Sunil K
Annual ACM IEEE Design Automation Conference: Proceedings of the 21st conference on Design automation; 25-27 June 1984. 1984. | Conference Proceeding
 
A novel clocking technique for VLSI circuit testability
Agrawal, Vishwani D
IEEE Journal of Solid-State Circuits, vol. 19, (no. 2), pp. 207-212, 1984. | Journal Article
 
Characterizing the LSI yield equation from wafer test data.
Seth, Sharad C and Agrawal, Vishwani D
IEEE TRANS. COMP. AIDED DESIGN INTEGRATED CIRCUITS SYST., vol. CAD-3, (no. 2), pp. 123-126, 1984. | Journal Article
 
Characterizing the LSI Yield Equation from Wafer Test Data
Seth, Sharad C and Agrawal, Vishwani D
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 3, (no. 2), pp. 123-126, 1984. | Journal Article
 
Chip layout optimization using critical path weighting
Dunlop, A. E⋅Agrawal, Vishwani D⋅Deutsch, D. N⋅Jukl, M. F⋅Kozak, P. and Wiesel, M.
Annual ACM IEEE Design Automation Conference: Proceedings of the 21st conference on Design automation; 25-27 June 1984. 1984. | Conference Proceeding
 
Novel clocking technique for VLSI circuit testability.
Mercer, Melvin R and Agrawal, Vishwani D
IEEE J. SOL. ST. CIRCUITS., vol. SC-19, (no. 2), pp. 207-212, 1984. | Journal Article
1983
Test generation for MOS circuits using D-algorithm
Jain, Sunil K and Agrawal, Vishwani D
Annual ACM IEEE Design Automation Conference: Proceedings of the 20th conference on Design automation; 27-29 June 1983. 1983. | Conference Proceeding
1982
Fault Coverage Requirement in Production Testing of LSI Circuits.
Agrawal, Vishwani D⋅Agrawal, Prathima and Seth, S. C
IEEE J. SOL. ST. CIRCUITS., vol. SC-17, (no. 1), pp. 57-61, 1982. | Journal Article
1981
Forecasting reject rate of tested LSI chips
Seth, Sharad C and Agrawal, Vishwani D
IEEE Electron Device Letters, vol. 2, (no. 11), pp. 286-287, 1981. | Journal Article
 
Forecasting Reject Rate of Tested LSI Chips.
Seth, Sharad C and Agrawal, Vishwani D
IEEE Electron Device Letters, vol. EDL-2, (no. 11), pp. 286-287, 1981. | Journal Article
 
Information Theoretic Approach to Digital Fault Testing
Agrawal, Vishwani D
IEEE TRANS. COMP., vol. C-30, (no. 8), pp. 582-587, 1981. | Journal Article
 
LSI product quality and fault coverage
Agrawal, Vishwani D⋅Seth, Sharad C and Agrawal, Prathima
Annual ACM IEEE Design Automation Conference: Proceedings of the 18th conference on Design automation : Nashville, Tennessee, United States; 29 June-01 July 1981. 1981. | Conference Proceeding
1978
Grating-lobe suppression in phased arrays by subarray rotation
Agrawal, Vishwani D
IEEE, Proceedings, vol. 66, pp. 347-349, 1978. | Journal Article
1974
Scanning transients in phased-array antennas
Agrawal, Vishwani D and ARORA, R. K
IEEE, Proceedings, vol. 62, pp. 850, 851, 1974. | Journal Article
1971
MUTUAL COUPLING IN PHASED ARRAYS OF RANDOMLY SPACED ANTENNAS (Dissertation)
Agrawal, Vishwani D (1971).