248 Publications (Page 7 of 10)
1997
Algorithms for switch level delay fault simulation
Bose, Soumitra⋅Agrawal, Vishwani D and Szymanski, Thomas G
IEEE INT TEST CONF TC. pp. 982-991. 1997, 1997. | Journal Article
 
Editorial
Agrawal, Vishwani
Journal of Electronic Testing : (JETTA), vol. 10, (no. 3), pp. 171, Jun 1997. | Journal Article
 
Editorial
Agrawal, Vishwani
Journal of Electronic Testing : (JETTA), vol. 10, (no. 1-2), pp. 5, Feb 1997. | Journal Article
 
Editorial
Agrawal, Vishwani
Journal of Electronic Testing : (JETTA), vol. 11, (no. 1), pp. 5, Aug 1997. | Journal Article
 
Editorial
Agrawal, Vishwani
Journal of Electronic Testing : (JETTA), vol. 11, (no. 2), pp. 107, Oct 1997. | Journal Article
 
Editorial
Agrawal, Vishwani
Journal of Electronic Testing : (JETTA), vol. 11, (no. 3), pp. 195, Dec 1997. | Journal Article
 
Effective path selection for delay fault testing of sequential circuits
Chakraborty, Tapan J and Agrawal, Vishwani D
IEEE INT TEST CONF TC. pp. 998-1003. 1997, 1997. | Journal Article
 
Fast identification of untestable delay faults using implications
Heragu, Keerthi⋅Patel, Janak H and Agrawal, Vishwani D
IEEE ACM INT CONF COMPUT AIDED DES DIG TECH PAP. pp. 642-647. 1997, 1997. | Journal Article
 
Flags and algebra for sequential circuit VNR path delay fault test generation
Srinivas, M. K⋅Bushnell, Michael and Agrawal, Vishwani D
The 1997 10th International Conference on VLSI Design; Hyderabad; India; 04-07 Jan. 1997. 1997. | Conference Proceeding
 
Low-power design by hazard filtering
Agrawal, Vishwani D
The 1997 10th International Conference on VLSI Design; Hyderabad; India; 04-07 Jan. 1997. 1997. | Conference Proceeding
 
On variable clock methods for path delay testing of sequential circuits
Chakraborty, T. J⋅Agrawal, Vishwani D and Bushnell, Michael
IEEE TRANS COMPUT AIDED DES INTEGR CIRCUITS SYST, vol. 16, (no. 11), pp. 1237-1249, 1997. | Journal Article
 
Redundancy removal and test generation for circuits with non-Boolean primitives
Chakradhar, S. T⋅Rothweiler, S. G and Agrawal, Vishwani D
IEEE TRANS COMPUT AIDED DES INTEGR CIRCUITS SYST, vol. 16, (no. 11), pp. 1370-1377, 1997. | Journal Article
 
Scheduling tests for VLSI systems under power constraints
Chou, R. M⋅Saluja, Kewal K and Agrawal, Vishwani D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, (no. 2), pp. 175-185, 1997. | Journal Article
 
SIGMA:a simulator for segment delay faults
Heragu, Keerthi⋅Patel, Janak H and Agrawal, Vishwani D
International Conference on Computer Aided Design: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design; 10-14 Nov. 1996. 1997. | Conference Proceeding
1996
Characteristic polynomial method for verification and test of combinational circuits
Agrawal, Vishwani D and Lee, David
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
Design for high-speed testability of stuck-at faults
Chakraborty, Tapan J and Agrawal, Vishwani D
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
Exact non-enumerative fault simulator for path-delay faults
Gharaybeh, Marwan A⋅Bushnell, Michael and Agrawal, Vishwani D
The 1996 IEEE International Test Conference; Washington, DC; USA; 20-24 Oct. 1996. 1996. | Conference Proceeding
 
Improving accuracy in path delay fault coverage estimation
Heragu, Keerthi⋅Patel, Janak H and Agrawal, Vishwani D
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
Improving Circuit Testability by Clock Control
Einspahr, Kent L⋅Seth, Sharad C and Agrawal, Vishwani D
Great Lakes Symposium on VLSI: Proceedings of the 6th Great Lakes Symposium on VLSI; 22-23 Mar. 1996. 1996. | Conference Proceeding
 
On test coverage of path delay faults
Majhi, Ananta K⋅Jacob, James⋅Patnaik, Lalit M and Agrawal, Vishwani D
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
Parallel concurrent path-delay fault simulation using single-input change patterns
Gharaybeh, Marwan A⋅Bushnell, Michael and Agrawal, Vishwani D
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
SIGMA: A simulator for segment delay faults
Heragu, Keerthi⋅Agrawal, Vishwani D and Patel, Janak H
The 1996 IEEE/ACM International Conference on Computer-Aided Design; San Jose, CA; USA; 10-14 Nov. 1996. 1996. | Conference Proceeding
 
Statistical path delay fault coverage estimation for synchronous sequential circuits
Pappu, Lakshminarayana⋅Bushnell, Michael⋅Agrawal, Vishwani D and Srinivas, M. K
The 1996 9th International Conference on VLSI Design; Bangalore; India; 03-06 Jan. 1996. 1996. | Conference Proceeding
 
Synthesis of self-testing finite state machines from high-level specification
Agrawal, Vishwani D⋅Blanton, R. D and Damiani, Maurizio
The 1996 IEEE International Test Conference; Washington, DC; USA; 20-24 Oct. 1996. 1996. | Conference Proceeding
1995
A partition and resynthesis approach to testable design of large circuits
Kanjilal, S.⋅Chakradhar, S. T and Agrawal, Vishwani D
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, (no. 10), pp. 1268-1276, 1995. | Journal Article