13 Grants
2023
Collaborative Research: An Effective and Efficient Low-Cost Alternate to Cell Aware Test Generation for Cell Internal Defects
Singh, Adit
National Science Foundation (NSF), Direct For Computer & Info Scie & Enginr, Division of Computing and Communication Foundations (ID: 2331003), $300,000USD, 2023-10-01 -- 2026-09-30
2019
SHF: Small: Minimizing System Level Testing of Processor SOCs
Singh, Adit
National Science Foundation (NSF), Direct For Computer & Info Scie & Enginr, Division of Computing and Communication Foundations (ID: 1910964), $499,939USD, 08/01/2019 -- 07/31/2022
2015
SHF: Small: Targeting Hazard Activated Faults to Improve Open Defect Coverage of Scan Delay Tests
Singh, Adit
National Science Foundation (NSF), Direct For Computer & Info Scie & Enginr, Division of Computing and Communication Foundations (ID: 1527049), $449,846USD, 06/15/2015 -- 05/31/2018
2013
COLLABORATIVE RESEARCH: TIMING VARIATION RESILIENT SIGNAL PROCESSING: HARDWARE-ASSISTED CROSS-LAYER ADAPTATION
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computer and Communication Foundations (ID: 1319529), $205,029USD, 09/01/2013 -- 08/31/2016
2009
Collaborative Research: Targeting Multi-Core Clock Performance Gains in the face of Extreme Process Variations
Singh, Adit
National Science Foundation (NSF), Directorate for Engineering, Electrical, Communications and Cyber Systems (ID: 0903449), $153,846USD, 09/15/2009 -- 08/31/2013
2008
EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computer and Network Systems (ID: 0834620), $220,000USD, 09/15/2008 -- 08/31/2012
 
Silicon Calibrated Scan Based Timing Tests for Delay Defect Detection
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computing and Communication Foundations (ID: 0811454), $350,000USD, 09/01/2008 -- 08/31/2012
2007
Collaborative Research: CRI: IAD: Electronic Testing Education, Research and Training Infrastructure
Nelson, Victor⋅Singh, Adit⋅Agrawal, Vishwani⋅Stroud, Charles and Dai, Fa
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computer and Network Systems (ID: 0708962), $642,995USD, 10/01/2007 -- 09/30/2011
2003
ITR: Built-In Test of High Speed/RF Mixed Signal Electronics
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computing and Communication Foundations (ID: 0325426), $233,536USD, 08/15/2003 -- 07/31/2007
2000
Wafer Oriented Trend Analysis for VLSI Test Opitmazation
Nelson, Victor and Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computing and Communication Foundations (ID: 9912389), $315,117USD, 09/01/2000 -- 08/31/2004
1992
Exploiting Defect Clustering Information in VLSI Testing
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computing and Communication Foundations (ID: 9208929), $140,130USD, 10/01/1992 -- 03/31/1996
1988
International Workshop on Defect and Fault Tolerance in VLSI Systems; October 6-7, 1988; Springfield, Massachusetts
Singh, Adit and Koren, Israel
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computer and Communication Foundations (ID: 8803418), $5,500USD, 07/01/1988 -- 12/31/1988
 
Research Initiation: Fault Tolerance Schemes for High Performance WSI Processor Arrays
Singh, Adit
National Science Foundation (NSF), Directorate for Computer & Information Science & Engineering, Division of Computer and Communication Foundations (ID: 8808325), $59,994USD, 06/01/1988 -- 11/30/1990