14 Publications
2018
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits
Burchard, JanErb, DominikReddy, Sudhakar MSingh, Adit D and Becker, Bernd
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, (no. 10), pp. 2165, 2018-Oct.. | Journal Article
 
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
Guin, UjjwalGuin, UjjwalGuin, UjjwalZhou, ZiqiZhou, ZiqiZhou, ZiqiSingh, AditSingh, Adit and Singh, Adit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, (no. 5), pp. 830, 2018-May. | Journal Article
2017
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging
Srivastava, AnkushSingh, VirendraSingh, Adit and Saluja, Kewal
Journal of Electronic Testing, vol. 33, (no. 6), pp. 739, 20171200. | Journal Article
2006
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
Dhillon, YSDiril, AUChatterjee, Abhijit and Singh, Adit D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, (no. 5), 2006. | Journal Article
 
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)
Yan, H. and Singh, Adit D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, (no. 11), 2006. | Journal Article
 
Combining negative binomial and Weibull distributions for yield and reliability prediction
Barnett, T. SGrady, M.Purdy, K. G and Singh, Adit D
IEEE Design & Test of Computers, vol. 23, (no. 2), pp. 110-116, 2006. | Journal Article
 
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects
Xuan, XiangdongSingh, Adit D and Chatterjee, Abhijit
Journal of Electronic Testing, vol. 22, (no. 4-6), pp. 471-482, 2006. | Journal Article
 
New JETTA Editors, 2006
Al-Hashimi, BashirGizopoulos, DimitrisSachdev, Manoj and Singh, Adit
Journal of Electronic Testing, vol. 22, (no. 1), pp. 10, 20060200. | Journal Article
2005
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
Diril, A. UDhillon, Y. SChatterjee, Abhijit and Singh, Adit D
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, (no. 9), pp. 1103-1107, 2005. | Journal Article
 
Pseudo Dual Supply Voltage Domino Logic Design
Diril, Abdulkadir UDiril, AbdulkadirDhillon, YuvrajDhillon, Yuvraj SChatterjee, AbhijitChatterjee, AbhijitSingh, Adit D and Singh, Adit
Journal of Low Power Electronics, vol. 1, (no. 2), pp. 152, August 2005. | Journal Article
1997
Incorporating I .sub.DDQ Testing with BIST for Improved Coverage: An Experimental Study
Weber, Walter and Singh, Adit
Journal of Electronic Testing, vol. 11, (no. 2), pp. 147, 19971001. | Journal Article
1989
Precharged CMOS quaternary logic encoder-decoder circuits
SINGH, ADIT D
International Journal of Electronics, vol. 67, (no. 5), pp. 817, 11/1/1989. | Journal Article
1987
Four-valued interface circuits for NMOS VLSI
SINGH, ADIT D
International Journal of Electronics, vol. 63, (no. 2), pp. 279, 8/1/1987. | Journal Article
1982
THE DESIGN OF PERIODICALLY SELF RESTORING REDUNDANT SYSTEMS (Dissertation)
Singh, Adit D (1982).